1. Field of the Invention
This invention relates to the recovery of source-synchronous digital data in a receiver and, more particularly, to algorithms for recovering a clock signal corresponding to the digital data signal in the presence of environmentally induced changes in clock frequency and phase.
2. Description of the Related Art
Source-synchronous communication links in which a clock is recovered from a data stream are increasingly common elements of high-speed data interfaces. A number of well-known techniques may be used to recover a clock signal from a data signal including a variety of phase-locked loop and delay-locked loop designs. Once a clock has been recovered, it may be used to resample the incoming data. Preferably, the phase of the recovered clock is adjusted so that the received data signal is sampled near the mid-point between bit transitions so as to maximize timing margin and minimize the bit-error-rate (BER). Uncorrected jitter in the phase of the recovered clock tends to move the sampling point away from the ideal point in the received data signal, resulting in poor timing margins and/or a higher BER. Consequently, the speed at which a communications link can operate is related to the accuracy of both the frequency and phase of the recovered clock.
In order to adjust the phase of the recovered clock, transition points in the received data signal may be compared to transitions in the recovered clock. Various well-known sampling circuits may be employed to compare the timing of transitions of the received data with the transitions of the recovered clock. These sampling circuits typically produce a phase error signal indicating whether a given bit transition is early or late as compared to the recovered clock. Information contained in the phase error signal may then be used to adjust the phase of the recovered clock so that the phase error is minimized. However, phase error signals are sensitive to jitter sources such as environmental fluctuations that affect the phase and frequency of data and clock signals. Consequently, it is desirable to detect and correct these fluctuations. Unfortunately, phase error signals may also be sensitive to jitter induced by random bit patterns in the incoming data. Therefore, it may also be desirable to minimize the sensitivity of phase corrections to these bit patterns. Accordingly, phase error signals are typically filtered prior to being used to adjust the phase of the recovered clock.
In view of the above, effective systems and methods of filtering phase error signals to reduce their sensitivity to random bit patterns while accurately tracking phase errors caused by environmental changes are desired.